3rd year online test: Computer Architecture Lab

Technical Grooming session for 3rd  year


Any VHDL description contain atleast one entity

  • yes
  • No

What can be the various uses of VHDL

  • To synthesize digital circuits
  • To verify and validate digital designs
  • To generate test vectors to test circuits
  • To simulate circuits

VHDL stands for

What are the Various levels of abstractions in VLSI design?

What is the symbol used for signal assignment?

  • ==
  • =
  • >=
  • <=