Digital Circuits and Systems-II Lab

The course is about learning the designing of basic circuits of digital electronics using VHDL.

Introduction to Digital Circuits and Systems

Introduction

DCS-II is extended version of DCS-I and include analysis and simulation of basic digital circuits on software platform while in DCS-I it was on Bread Board. The preferred language  for programming is VHDL and students will practice and learn this language in this lab. VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language. VHDL was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment.

The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that the logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of VHDL borrows heavily from the Ada programming language in both concepts and syntax.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string. A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_logic and its vector version std_logic_vector. The updated IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.

In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to work on the next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was published in January 2009.

Course Goals and Objectives

The primary objective of this Lab is to analyze and simulate various Digital Circuits by means of a language named as VHDL on Xilinx platform. To start with, the students will be introduced to the concept of VHDL programming language and various modeling techniques like structural modeling, behavioral modeling and dataflow modeling.  Along with VHDL, introduction to Xilinx software is to be done to get familiar with it. The basic steps of programming, like compilation and simulation with ISIM is to be done. Initially students can be prepared for programming by using user templates provided in Xilinx version 11.2 so that they can do further programming very well. The students, lab assistant, and faculty coordinator all have certain responsibilities towards successful completion of the lab's goals and objectives.

Prerequisite for the course

The software ued in this lab have some basic steps like programming, compilation and simulation. To work with this software, main requirement is the knowledge of basics of Digital Circuits and Systems which students have gone through in 4th semester as they have the same subject in their curriculum. One other requirement is knowledge of VHDL which will be covered in theory by the respective teacher. The knowledge on the following basic concepts is prerequisite for the lab:

Digital Circuits,

Basic Gates and Universal Gates

Isim Software

Basic knowledge of VHDL;

Do’s & Don’ts

Login on to the students’ Login (if necessary).

Internet facility is available in the Lab, but students may use it after getting permission from the instructor.

No food stuffs are allowed in the Lab.

A group of maximum four students is allowed to work on a setup.

Students need to take A-4 size sheets for taking the printout of the experiments.

Arrange the chairs while leaving the lab.

Maintain the cleanliness in the lab.


Write a VHDL code for implementation of all Basic and Universal Gates .

Dataflow Modelling For OR Gate

library ieee;

use ieee.std_logic_1164.all;

entity orgate is

port(A, B:in bit; C:out bit);

end orgate;

architecture dataflow of orgate is

begin

C<=A or B;

end dataflow;

OR Gate : Behavioral Modeling


library ieee;

use ieee.std_logic_1164.all;

entity or2 is

port(a,b:in bit;c:out bit);

end or2;

architecture behavior of or2 is

begin

sum:process(a,b)

begin

if(a='0'and b='0')then

c<='0';

else c<='1';

end if;

end process;

end behavior;

NAND Gate: Dataflow Modeling

library ieee;

use ieee.std_logic_1164.all;

entity nandgate is

port(A,B:in bit;C:out bit);

end nandgate;

architecture dataflow of nandgate is

begin

C<=A nand B;

end dataflow;

NAND Gate : Behavioral Modeling

library ieee;

use ieee.std_logic_1164.all;

entity nand2 is

port(a,b:in bit;c:out bit);

end nand2;

architecture behavior of nand2 is

begin

sum:process(a,b)

begin

if(a='1'and b'1')then

c<='0';

else c<='1';

end if;

end process;

end behavior;

XOR Gate: Dataflow Modeling

library ieee;

use ieee.std_logic_1164.all;

entity xorgate is

port(A,B:in bit;C:out bit);

end xorgate;

architecture dataflow of xorgate is

begin

C<=A xor B;

end dataflow;

XOR Gate : Behavioral Modeling

library ieee;  

use ieee.std_logic_1164.all;

entity xor2 is

port(a,b:in bit;c:out bit);

end xor2;

architecture behavior of xor2 is

begin

process(a,b)

begin

if(a='0'and b='0')then

c<='0';

elsif(a='0'and b='1')then

c<='1';

elsif(a='1'and b='0')then

c<='1';

elsif(a='1'and b='1')then

c<='0';

end if;

end process;

end behavior;

Write Code for XNOR GATE, AND Gate, NOT GATE, NOR GATE.

VHDL code using Behavioral modeling: a. Half Adder, b. Full Adder, c. Half Subtractor, d. Full Subtractor using Gates and Truth Table.

Code for Half Adder : Dataflow Modelling

library ieee;

use ieee.std_logic_1164.all;

entity ha_adder is

port(A,B:in bit;S,C:out bit);

end ha_adder;

architecture dataflow of ha_adder is

begin

S<=A XOR B ;

C<=A AND B;

end DATAFLOW;

.

Code for Half Adder : Behavioral Modelling

library ieee;

use ieee.std_logic_1164.ALL;

entity ha is

port(A,B: in bit; S,C:out bit);

end ha;

architecture ha1 of ha is

begin

process (A,B)

begin

if A='0' and B='0'

then S<='0'; C<='0';

elsif A='0' and B='1'

then S<='1'; C<='0';

elsif A='1' and B='0'

then S<='1'; C<='0';

else  S<='0'; C<='1';

end if;

end process;

end ha1;

Code for Half Adder : Structural Modeling using gatesUntitled content

library ieee;

use ieee.std_logic_1164.all;

entity ha is

 port(A,B:in bit;S,C:out bit);

end ha;

architecture structural of ha is

component andg

 port(A,B:in bit;C:out bit);

end component;

component xorg

 port(A,B:in bit;S:out bit);

end component;

begin

a1 : andgate port map(A,B,C);

a2 : xorgate port map(A,B,S);

end structural;

Code for Full Adder : Dataflow Modelling

library ieee;

use ieee.std_logic_1164.all;

entity full_adder is

port(A,B,Cin:in bit; S,Cout:out bit);

end full_adder;

architecture dataflow of full_adder is

begin

S<= A xor B xor Cin;

Cout<= (A and B) or (B and Cin) or (A and Cin);

end dataflow;

Code for Full Adder : Behavioral Modelling

library ieee;

use ieee.std_logic_1164.all;

entity f_adr1 is

port(A,B,Cin:in bit;S,Cout:out bit);

end f_adr1;

architecture structural of f_adr1 is

begin

process ( A, B, Cin)

and B='0' and Cin='0')then

S<='0';Cout<='0';

elsif(A='0' and B='0' and Cin='1')then

S<='1';Cout<='0';

elsif(A='0' and B='1' and Cin='0')then

S<='1';Cout<='0';

elsif(A='0' and B='1' and Cin='1')then

S<='0';Cout<='1';

elsif(A='1' and B='0' and Cin='0')then

S<='1';Cout<='0';

elsif(A='1' and B='0' and Cin='1')then

S<='0';Cout<='1';

elsif(A='1' and B='1' and Cin='0')then

S<='0';Cout<='1';

elsif(A='1' and B='1' and Cin='1')then

S<='1';Cout<='1';

end if;

end process;

end behavior;

Full Adder: Structural Modeling using half adder

library ieee;

use ieee.std_logic_1164.all;

entity f_adrstr is

port(A,B,Cin:in bit;S,Cout:out bit);

end f_adrstr;

architecture structural of f_adrstr is

component ha_adder

Port(A,B:in bit;S,C:out bit);

end component;

component orgate

port(A,B:in bit;C:out bit);

end component;

signal s1,c1,c2:bit;

begin

h1:ha_adder port map(A,B,s1,c1);

h2:ha_adder port map(s1,Cin,S,c2);

o1:orgate port map(c1,c2,Cout);

end structural; 

 

Dataflow VHDL code for Half Subtractor

library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

entity hs1 is

     Port ( A,B : in  bit;

            Diff,bor : out  bit);

 end hs1;

 architecture Dataflow of hs1 is

 begin

 diff<=A xor B;

 bor<=(not A) and B;

 end Dataflow;

Behavioral VHDL code for Half Subtractor

library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

 entity h_sub1 is

     Port ( a,b : in bit;diff,bor : out bit);     

 end h_sub1;

 architecture Behavioral of h_sub1 is

 begin

process(a,b)

begin

if(a=b)then

diff<='0';bor<='0';

elsif(a='0' and b='1')then

diff<='1';bor<='1';

elsif(a='1' and b='0')then

diff<='1';bor<='0';

end if;

end process;

end Behavioral;

Structural VHDL code for Half Subtractor

library ieee;

use ieee.std_logic_1164.all;

entity ha_sub is

 port(A,B:in bit;Diff,Bor:out bit);

end ha_sub;

architecture structural of ha_sub is

component xorg

 port(a,b:in bit;c:out bit);

end component;

component notg

 port(a:in bit;c:out bit);

end component;

component andg

 port(a,b:in bit;c:out bit);

end component;

signal s1:bit;

begin

a1 : xorg port map(a=>A,b=>B,c=>Diff);

a2 : notg port map(a=>A,c=>s1);

a3 : andg port map(a=>s1,b=>B,c=>Bor);

end structural;

 

 

 

Write code for full subtractor.

VHDL code to design (a) 4:1 Multiplexer and 1: 4 Demultiplexer using “if statement” , “case statement”. (b) 16:1 Multiplexer using 4:1 Multiplexer

4x1: Mux: Behavioral Modeling using “ if statement ”

library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

 use IEEE.STD_LOGIC_ARITH.ALL;

 use IEEE.STD_LOGIC_UNSIGNED.ALL;

 entity mux1 is

     Port ( I0,I1,I2,I3 : in bit;

            S0,S1 : in  bit;

            Y : out  bit);

 end mux1;

 architecture Behavioral of mux1 is

 begin

 process(I0,I1,I2,I3,S0,S1)

 begin

 if(S1='0' and S0='0')then

 Y<=I0;

 elsif(S1='0' and S0='1')then

 Y<=I1;

 elsif(S1='1' and S0='0')then

 Y<=I2;

 elsif(S1='1' and S0='1')then

 Y<=I3;

 end if;

 end process;

 end Behavioral;

4x1: Mux :Behavioral VHDL code using “case statement”

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX41 is

    Port ( x : in std_logic_vector(3 downto 0);

           y : out std_logic;

           s : in std_logic_vector(1 downto 0));

end MUX41;

architecture MUX of MUX41 is

begin

process(x,s)

begin

case s is

when "00"=>y<=x(0);

when "01"=>y<=x(1);

when "10"=>y<=x(2);

when others=>y<=x(3);

end case;

end process;

end MUX;

 

 

 

 

 

 

 

 

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4x1: Mux: structural Modeling using gates

library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

 entity mux4x1_str is

     Port ( I0,I1,I2,I3 :in bit;

            S0,S1 :in bit;

            Y :out bit);

 end mux4x1_str;

 architecture structural of mux4x1_str is

component notg

port(a:in bit;b:out bit);

end component;

component andg

port(a,b,c:in bit;d:out bit);

end component;

component org

port(a,b,c,d:in bit;e:out bit);

end component;

signal x1,x2,x3,x4,x5,x6:bit;

begin

a1:notg port map(a=>S0,b=>x1);

a2:notg port map(a=>S1,b=>x2);

a3:andg port map(a=>I0,b=>x2,c=>x1,d=>x3);

a4:andg port map(a=>I1,b=>x2,c=>S0,d=>x4);

a5:andg port map(a=>I2,b=>S1,c=>x1,d=>x5);

a6:andg port map(a=>I3,b=>S1,c=>S0,d=>x6);

a7:org port map(a=>x3,b=>x4,c=>x5,d=>x6,e=>Y);

end structural;

 

16:1 Structural Modeling using 4:1 Multiplexer

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_16x1 is

    Port ( I : in bit_vector(0 to 15);

           Y : out bit;

           S : in bit_vector(0 to 3));

end MUX_16x1;

architecture str of MUX_16x1 is

component mux1

Port (i0, i1, i2, i3, a, b: IN bit;

        y : OUT bit);

end component;

signal Y0,Y1,Y2,Y3:bit;

begin

m1: mux1 port map(I(0),I(1),I(2),I(3),S(0),S(1),C0);

m2: mux1 port map(I(4),I(5),I(6),I(7),S(0),S(1),C1);

m3: mux1 port map(I(8),I(9),I(10),I(11),S(0),S(1),C2);

m4: mux1 port map(I(12),I(13),I(14),I(15),S(0),S(1),C3);

m5: mux1 port map(Y0,Y1,Y2,Y3,S(2),S(3),Y);

end str;

 

 

Write code for demultiplexer using behavioral and structural modelling.

Write VHDL code to design a. Octal to Binary Encoder, b. 2 to 4 Decoder c. 4 bit Parity Checker d. 3 to 8 Decoder using 2:4 Decoders by Structural Modeling.

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